As is known, some applications require logic components providing a high signal transmission speed. This high speed is generally achieved by using the technique of salicidation comprising forming a layer of self-aligned metallic silicide (known as "salicide" from "self-aligned silicide") on the junctions with the purpose of reducing the resistivity thereof. The silicide layer is formed by depositing a metal layer (preferably of titanium (TiSi.sub.2), cobalt or titanium-cobalt) on the entire surface of the device and carrying out a heat treatment step that causes the metal to react with the silicon, left bare on the junctions and the gate regions, and causes the formation of metallic silicide in those regions. The metal does not react on the zones of the device which are covered by silicon oxide. The metal that has not reacted is then removed by etching with a suitable solution which leaves the metallic silicide intact. In this way both the gate regions of multicrystal silicon and the junctions come to have in parallel a metallic silicide layer of low resistivity (approx. 3/4 .mu..OMEGA./square) which permits a reduction of the series resistance to the transistors and the short-circuiting of the source regions of the transistors with the substrate contacts without using metallic interconnections, providing greater freedom in the positioning of the contacts to the transistors. The "salicide" technique is described, for example, in the article "Application of the self-aligned titanium silicide process to very large-scale integrated n-metal-oxide-semiconductor technologies" by R. A. Haken in J. Vac. Sci. Technol. B, Vol. 3, No. 6, November/December 1985 and in "Self-aligned silicidation for sub half micron technologies" by K. Maex, Conference Proceedings, ULSI-X, 1995, pp. 405-414.
There are also various families of devices (non-volatile memories, smart cards etc.) for which resistors with high resistance values are required; on the other hand, manufacture of such resistors is particularly complex in processes in which the salicidation of the junctions is required at the same time.
In fact, current processes for manufacturing lightly doped and high precision resistors provide for forming LDD (Lightly Doped Drain) transistors in which source and drain junctions are formed with a gradual profile by a first implant of ionic dopants that is lighter and self-aligned with the gate and a second, heavier, implant self-aligned with spacer elements. The lightly doped precision resistors are formed during the first implant, self-aligned with a polysilicon ring; the second heavy implant is then screened in the zone of the resistors by a suitable mask. The heavy implant is made only in the region around the contact to ensure a good contact.
The salicidation process presents problems if the underlying silicon is lightly doped and is not therefore compatible with forming lightly doped resistors. Furthermore, the resistance is greatly reduced if salicide is present. This implies that it is necessary to avoid the salicidation of lightly doped resistors.